The present invention relates to a digital signal input circuit and a method of testing it, and more particularly to an input interface circuit to which a high-speed and small-amplitude digital signal is applied.
For example, a personal computer includes functional IC blocks such as a CPU, a memory controller and a memory. The memory controller controls an access from the CPU or the other device to the memory. The transfer of data between the CPU and the memory controller and the transfer of data between the memory controller and the memory are performed through buses, respectively.
Data received by each of these or similar IC blocks from the other IC block is in the form of a high-speed and small-amplitude digital signal. Since the amplitude of the signal is too small, the data cannot be handled by a circuit in the IC block as it is. Especially, if an inputted digital signal includes noise superimposed thereon, the determination of a logical level thereof will be difficult. Accordingly, it is common that an input portion of the IC block such as a memory controller or a memory is provided with an input interface circuit which performs discrimination and waveform shaping of an inputted digital signal.
Many conventional input interface circuits includes a combination of a current mirror type differential amplifier and a latch circuit. In this interface circuit, a logical level of an input signal having a small peak-to-peak voltage of, for example, about 0.8 V is discriminated through the comparison thereof with a reference signal by use of the current mirror type differential amplifier, the discriminated input signal is amplified up to a voltage of, for example, about 2.5 V to 3.0 V which can be handled by a digital circuit, and the amplified output signal is held by the latch circuit which is a digital circuit. The test of the operation of such a differential input type input interface circuit includes a test through which the judgement is made of whether or not a set-up operation from a point of time of stabilization of an output of the differential amplifier to a point of time when it can be held by the latch circuit falls within a specified set-up time.
The judgement is made on the basis of two criteria. One is concerned with the timing of the set-up operation, that is, whether or not a transistor in the input interface circuit has a sufficient driving capability for discrimination of a logical level in a prescribed time. The other is concerned with whether or not the sampling for the latch circuit of the input interface circuit is performed in the prescribed time.
For such a test of the operation of the input interface circuit, there has hitherto been used a memory tester which generates an analog signal having a linearly varying rise pattern and applies this analog signal to the input interface circuit in a manner such that the applied analog signal is sequentially shifted by a short time to measure a time until a normal operation is no longer available.
However, the conventional tester provided with the above-mentioned function of generating an analog signal capable of short-time shifts has a complicated circuit structure and is therefore high in cost. Accordingly, an input interface circuit completed through a test using such a costly tester becomes expensive.
Further, JP-A-8-63268 (laid open on Mar. 8, 1996) has disclosed an input/output interface circuit provided with an integrating circuit. However, no reference is made to the test of that circuit.